The present invention relates to a semiconductor device used for high density packaging, multi-chip module, bare chip packaging, and the like, and a packaging structure of the semiconductor device.
In recent years, the reduced sizes and increased performances of the electronic devices will generate the demand for higher integration, higher density, and higher processing speed of semiconductor devices used for the electronic devices. To meet such a demand, packages of semiconductor devices are being developed from a pin insertion type to a surface packaging type for increasing the packaging densities, and also developed from a DIP (Dual Inline Package) type to a QFP (Quad Flat Package) type and a PGA (Pin Grid Array) type for coping with the multi-pin arrangement.
Of the packages thus developed, the QFP is difficult to cope with the multi-pin arrangement because it is so configured that leads to be connected to a packaging substrate are concentrated only at a peripheral portion of the package and are also liable to be deformed due to finer diameters thereof. Besides, the PGA has a limitation in coping with both high speed processing and surface packaging because it is so configured that terminals to be connected to a packaging substrate are elongated and very collectively arranged.
Recently, to solve these problems and to realize a semiconductor device capable of coping with high speed processing, a BGA (Ball Grid Array) package is disclosed in U.S. Pat. No. 5,148,265, which has ball-like connection terminals over the entire packaging surface of a carrier substrate electrically connected to a semiconductor chip by gold wire bonding. In this package, since the terminals to be connected to a packaging substrate are formed into ball-like shapes, they can be arranged in a dispersed manner over the entire packaging surface without such deformation of leads as found in the QFP, so that pitches between the terminals become larger, to thereby make surface packaging easy; and also since the lengths of the connection terminals are shorter than those of the PGA, an inductance component becomes smaller and thereby a signal transmission speed becomes faster, with a result that such a package is allowed to cope with high speed processing.
In the above-described BGA package, an elastic body is inserted as an interposer between a semiconductor chip and terminals of a packaging substrate for relieving a thermal stress produced due to a difference in thermal expansion between the packaging substrate and the semiconductor chip upon packaging thereof. The semiconductor device having such a structure, however, has problems depending on the use of gold wire bonding for connection with upper electrodes of the semiconductor chip; namely, since the connection portions connected to the gold wires are concentrated only at a peripheral portion of the chip, the structure has a spontaneous limitation in coping with the further increasing futuristic demand for multi-pin arrangement and higher processing speed of semiconductor devices and has also an inconvenience in terms of mass-production and improvement in production yield because of the increased number of production steps due to the complexity thereof.
Japanese Patent Laid-open No. Hei 5-326625 discloses an improved packaging structure of a flip-chip type package in which a LSI chip having solder bumps is mounted on a multi-layered wiring ceramic substrate having solder bumps, wherein a sealing member is filled between the LSI chip and the multi-layered wiring ceramic substrate as a carrier substrate. The above packaging structure, however, seems to have a problem in terms of higher density interconnection, higher response speed of signals, and miniaturization of the package, because the use of the ceramic substrate as multiple wiring layers makes it difficult to reduce a dielectric constant. Another problem of such a package resides in the production step requiring high temperature burning for ceramic, and in difficult handling of the brittle, thin ceramic substrate.
Objects of the present invention are to provide a semiconductor device capable of coping with the further increasing futuristic demand for high speed processing and high density packaging and being high in reliability in connection with a packaging substrate; and to provide a packaging structure of the semiconductor device.
The gist of the present invention made for solving the above-described problems is as follows:
(1) According to the present invention, there is provided a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof, and multiple wiring layers.
(2) According to the present invention, there is also provided a semiconductor device including: a multi-layered wiring structure having a conductive layer to be electrically connected to a packaging substrate, the structure being provided on the surface of a semiconductor chip on the packaging substrate side; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between the semiconductor chip and the packaging substrate after packaging thereof.
(3) According to the present invention, there is also provided a packaging structure connected to and mounted on the packaging substrate via the ball-like terminals disposed in a grid array.
The above-described multi-layered wiring structure is required to attain two purposes: to achieve electric connection between the semiconductor device and a packaging substrate when the semiconductor device is mounted on the packaging substrate; and to relieve a thermal stress produced between the semiconductor device and the packaging substrate upon packaging thereof. Accordingly, the features of the present invention reside in that
{circle around (1)} the above multi-layered wiring structure includes two components, that is, multiple wiring layers for transmitting an electric signal and a buffer layer for relieving a thermal stress; or
{circle around (2)} an interlayer insulating film in multiple wiring layers for transmitting an electric signal of the multi-layered wiring structure is made of a material for reliving a thermal stress produced between a semiconductor chip and a packaging substrate after packaging thereof, whereby serving as the function of the buffer layer.
The above multi-layered wiring structure is preferably composed of three or more layers including a conductive layer portion having a ground layer, power supply layer, and wiring layer. This makes it possible to increase a signal transmission speed and to reduce the occurrence of noise.
Each of the buffer layer and the insulating layer is preferably made of a material having a low dielectric constant. FIG. 1 shows a relationship between the dielectric constant and each of the thickness of the insulating layer and the transmission delay time. In addition, the film thickness h of the insulating layer is given by the following equation [1]. For example, for the wiring having a width w=50 xcexcm and a height t=30 xcexcm, the film thickness h at a characteristic impedance Z0=55 xcexa9 can be calculated by substituting these values in the equation [1].
The delay time Td can be given by substituting a dielectric constant xcex5r of the insulating layer in the following equation (2).                               Z          o                =                              60                                          ϵ                r                                              ⁢                      ln            ⁡                          (                                                1.9                  ⁢                                      xe2x80x83                                    ⁢                  h                                                  w                  ⁡                                      (                                          0.8                      +                                              t                        /                        w                                                              )                                                              )                                                          (        1        )            
Td=3.34 {square root over (xcex5r+L )}xe2x80x83xe2x80x83[2]
From the result shown in FIG. 1, it becomes apparent that the use of a low dielectric constant material enables thinning of the film thickness h of the insulating layer (that is, thinning of the semiconductor device) and also enables shortening of the delay time (that is, increase in response speed). For example, in the case where the insulating layer is made of alumina which is a typical material of a ceramic substrate, since alumina has a dielectric constant of 9.34, the film thickness h of the insulating layer becomes 606 xcexcm. On the contrary, in the case where the insulating layer is made of polyimide having a dielectric constant of 3.0, the film thickness thereof can be reduced to 180 xcexcm. With respect to the delay time Td of the insulating layer made of polyimide, it can be shortened by about one-half of that of the insulating layer made of alumina, that is, from 10.2 ns/m to 5.78 ns/m.
The above insulating layer is preferably made of a low thermal expansion polyimide having a linear expansion coefficient of 20 ppm/K or less or a silicon elastomer having an elastic modulus of 10 kg/mm2 or less. The use of these materials enables high speed transmission of an electric signal, thinning of the package, and reduction in stress of the package.
Specific examples of the above low thermal expansion polyimide may include a polyimide obtained by polymerization of pyromellitic acid dianhydride and any one of 2,5-diaminotoluene, diaminodurene, benzidine, 3,3xe2x80x2-dimethylbenzidine, 3,3 xe2x80x2-dimethoxybenzidine, 4,4xe2x80x2-diaminoterphenyl, 1,5-diaminonaphthalene, and 2,7-diaminofluorene; a polyimide obtained by polymerization of 3,3xe2x80x2, 4,4xe2x80x2-benzophenonetetracarboxylic acid dianhydride and any one of 3,3xe2x80x2-dimethylbenzidine, 4,4xe2x80x2-diaminoterphenyl, and 2,7-diaminofluorene; a polyimide obtained by polymerization of 3,3xe2x80x2, 4,4xe2x80x2-biphenyltetracarboxylic acid dianhydride and any one of paraphenylenediamine, 2,5-diaminotoluene, benzidine, 3,3xe2x80x2-dimethylbenzidine, 4,4xe2x80x2-diaminoterphenyl, 1,5-diaminonaphthalene, 2,7-diaminofluorene, and 2,5-diaminopyridine.
The present inventors have made the analysis of a thermal stress of a semiconductor device upon packaging thereof, and found that an elastic body having an elastic modulus of 10 kg/mm2 or less enables the relief of the thermal stress of the semiconductor device without any influence of the linear expansion coefficient of the elastic body. Accordingly, the object of the present invention can be attained by the use of an elastic body having an elastic modulus of 10 kg/mm2. When the elastic modulus of the above elastomer is more than 10 kg/mm2, the elastic body is affected by the linear expansion coefficient thereof, thereby reducing the stress reliving effect of the elastomer.
The elastic body having an elastic modulus of 10 kg/mm2 is preferably made of an elastomer or a low elastic engineering plastic.
Specific examples of the above elastomer may include fluorine rubber, silicon fluoride rubber, acrylic rubber, hydrogenated nitrilo rubber, ethylene propylene rubber, chlorosulfonated polystyrene rubber, epichlorohydrin rubber, butyl rubber, and urethane rubber.
Specific examples of the above low elastic engineering plastic may include polycarbonate (PC)/acrylonitrile butadiene styrene (ABS) alloy, polysiloxanedimethylterephthalate (PCT)/polyethyleneterephthalate (PET), copolymerized polybuthylene terephthalate) (PBT)/polycarbonate (PC) alloy, polytertafluoroethylene (PTFE), florinated ethylene propylene polymer (FET), polyalylate, polyamide (PA)/acrylonitrile butadiene styrene (ABS) alloy, modified epoxy resin, and modified polyolefin resin.
Other than the above plastics, there may be used a high molecular material selected from one or two or more kinds of thermosetting resins such as epoxy resin, unsaturated polyester resin, epoxyisocyanate resin, maleimide resin, maleimide epoxy resin, cyanic acid ester resin, cyanic acid ester epoxy resin, cyanic acid ester maleimide resin, phenol resin, diallyl phthalate resin, urethane resin, cyanamide resin, and maleimide cyanamide resin. Of these high molecular materials, to attain the object of the present invention, there may be preferably used those having such stable hardening characteristics as not to be hardened at room temperature but to be hardened by heating at a temperature of from 150 to 350xc2x0 C. for a period of from several minutes to several hours. Such a thermosetting resin is less in thermal deformation at a high temperature and is excellent in heat resistance.
The hardened material thus obtained is desired to have a dielectric strength of 10,000 V/cm or more, and to have a heat resistance withstanding a temperature of 150xc2x0 C. or more for a long period of time.
The above high molecular material before being hardened is preferably adjustable in its viscosity by a solvent, and more preferably, it exhibits such a photosensitive property as to be hardened by light emission or the like.
The multiple wiring layers of the present invention can be typically realized in accordance with either of two processes shown in FIGS. 2 and 3.
In the sequentially laminating process shown in FIG. 2, the semiconductor of the present invention can be fabricated in accordance with the following steps: first, forming a wiring layer by (a) forming an elastomer insulating layer 2 on a semiconductor chip 1, (b) forming windows 3 for interlayer connection in the insulating layer 2, and (c) forming a wiring layer by performing interlayer connection 4; secondarily, repeating the above steps by the number required for forming necessary layers, to form multiple wiring layers; and finally, (d) forming solder balls 5 as connection terminals to a packaging substrate on the multiple wiring layers.
In the film lamination process shown in FIG. 3, the semiconductor device of the present invention can be fabricated by the following steps: (e) sticking wiring sheet-like pieces 6 to each other, (f) forming windows 3 for interlayer connection in the laminated sheet-like pieces 6, (g) performing interlayer connection 4, to form a multi-layered wiring sheet, (h) adhesively bonding the multi-layered wiring sheet on a semiconductor chip via a multi-sword shaped conductor containing buffer layer 7, to form a multi-layered wiring structure, and finally forming solder bumps on the multi-layered wiring structure.
The above multi-sword shaped conductor containing buffer layer is prepared, for example, by piecing a polyimide film (thickness: about 50 xcexcm) adhesively bonded with a copper foil (thickness: about 18 xcexcm) at specified positions by excimer laser (KrF: 248 nm, pulse energy: 40 mj/pulse, repeated frequency: 600 Hz at maximum; average output: 24 W), to form holes (diameter: 25 xcexcm, hole pitch: 40 xcexcm); burying the holes with a conductive material by plating such as a known chemical copper plating, followed by etching back of the copper foil; applying nonelectrolytic tin plating on both ends of the conductive material buried in the holes, or by casting (for example, potting) an elastomer into a vessel in which a large number of gold wires are erected at specified positions; and adjusting the thickness of the elastomer containing the gold wires after hardening.
The multi-sword shaped conductor containing buffer layer can be formed of an anisotropic conductive film which has electric conduction only in the vertical direction. A semiconductor chip is superposed on one side surface of the film. At this time, with respect to the film, only portions connected to electrode portions of the semiconductor chip are made electrically conductive. On the other hand, a multi-layered wiring structure having electrodes corresponding to the electrode portions of the semiconductor chip is superposed on the other side surface of the film. At this time, with respect to the film, only portions connected to the electrodes of the multi-layered wiring structure are made electrically conductive.
The multi-sword shaped conductor containing buffer layer is connected to a semiconductor chip by Au/Sn bonding, Sn/Pb bonding, or the like. More specifically, gold is vapor-deposited at electrode portions, to be bonded to each other, of both the chip and buffer layer, followed by forming tin solders thereat by nonelectrolytic tin plating, and in such a state, both the chip and buffer layer are pressed to each other and heated (240-250xc2x0 C.) for several seconds (2-3 sec), to be thus bonded to each other by melting of the tin solders formed on the electrode portions. The connection of the buffer layer to the multi-layered wiring structure can be performed in the same manner as described above.
The ball-like terminals disposed in a grid array on the connection surface of the multi-layered wiring structure to a packaging substrate may be formed of a solder alloy containing tin, zinc or lead; silver; copper or gold into ball-shapes. In this case, such a ball made of the above metal may be covered with gold. By the use of such ball-like terminals, the semiconductor device can be electrically connected to a packaging substrate by melting of the ball-like terminals or by contact or vibration of the ball-like terminals without heating. Other than the above metals, the ball-like terminal may be formed of an alloy of one kind or two or more kinds selected from molybdenum, nickel, copper, platinum and titanium; or may be formed of multi-layered films having layers made of two or more kinds selected from the above metals.
The above semiconductor chip may include a linear IC, LSI, logic, memory, gate array, or the like having circuits formed on a semiconductor substrate.
In the present invention, the semiconductor device is provided with a heat spreader for assisting heat radiation produced upon operation of the semiconductor chip. The heat spreader is formed of a material excellent in thermal conductivity, for example, a metal having a high thermal conductivity, such as copper. In particular, the heat spreader is preferably configured to have a structure (see FIG. 7) in which the semiconductor chip 1 is buried and mounted. In the heat spreader having such a structure, a multi-layered wiring structure having an area larger than that of a semiconductor chip can be formed on the heat spreader. The heat spreader having this structure may include heat radiation fins provided on the portions other than the chip mounting surface for increasing the entire heat radiation surface area.
The semiconductor device of the present invention may be so configured that two or more of semiconductor chips are mounted on the single multi-layered wiring structure
According to the semiconductor device of the present invention, it is possible to dispose ball-like terminals to be connected to a packaging substrate over the entire packaging surface of the multi-layered wiring structure and to eliminate the necessity of gold wire bonding. As a result, when compared with the conventional semiconductor device, the semiconductor device of the present invention is allowed to easily cope with multi-pin arrangement, and therefore, it is suitable to higher density and higher integration.
In the semiconductor device of the present invention, since a distance between the ground layer and the power supply layer in the semiconductor substrate can be shortened and also the semiconductor chip can be directly connected to the multi-layered wiring structure without formation of solder bumps, the wiring distance can be shortened as compared with the conventional semiconductor device in which the semiconductor chip and the multi-layered wiring structure are soldered to each other by electrode bumps, with a result that an inductance component can be reduced and thereby a signal transmission speed becomes faster, leading to the increased processing speed of the semiconductor device. Also, in the present invention, the use of a low dielectric constant material (polyimide, elastomer, or the like) allows the package to be thinned more than that of the conventional package using the multi-layered ceramic substrate when compared at the same signal frequency
Additionally, in the present invention, the formation of the multi-layered wiring structure having a low elastic modulus on the semiconductor chip makes it possible to reduce a thermal stress produced between a packaging substrate and the semiconductor chip, and hence to improve the reliability in connection of the semiconductor chip to the packaging substrate after packaging thereof.